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Pull requests list

[ORC] Reimplement EPCGenericMemoryAccess on RTBridge proxies
#215160 opened Aug 10, 2026 by lhames Contributor Loading…
[KnownFPClass] Refine sNaN handling for asin/acos llvm:globalisel llvm:support llvm:transforms
#215159 opened Aug 9, 2026 by ZERICO2005 Contributor Loading…
2
[MachineCSE] Walk the terminator the hoisted copy is placed in front of backend:X86 llvm:codegen
#215158 opened Aug 9, 2026 by mattst88 Contributor Loading…
1
[Clang] Implement CWG 2282 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category
#215157 opened Aug 9, 2026 by igorkudrin Contributor Loading…
4
[GlobalISel][AArch64] Lower G_BITCAST vectors with non-integer element ratio backend:AArch64 llvm:globalisel
#215154 opened Aug 9, 2026 by varev-dev Contributor Loading…
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[AMDGPU] Suppress OpenCL rewriting of printf where it is not linked backend:AMDGPU
#215153 opened Aug 9, 2026 by jhuber6 Contributor Loading…
1
[CodeGen] Take the executable stack from a module flag backend:AArch64 backend:RISC-V backend:X86 flang:codegen flang:fir-hlfir flang Flang issues not falling into any other category llvm:codegen llvm:ir
#215152 opened Aug 9, 2026 by vtjnash Member Loading…
5
Fix: [lit] builtin cat/diff spawn-fallback leaked PYTHONPATH into later RUN lines llvm-lit testing-tools
#215151 opened Aug 9, 2026 by M001N Loading…
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2
[GlobalISel] Propagate fast-math flags when fusing fmul+fadd into fma backend:AMDGPU llvm:globalisel
#215150 opened Aug 9, 2026 by MrSidims Contributor Loading…
2
[NFC][AMDGPU] Use brackets in decode-err.txt backend:AMDGPU
#215148 opened Aug 9, 2026 by shiltian Contributor Loading…
3
[AMDGPU][MC] Fix out-of-range MFMA tuple register-name assertion backend:AMDGPU
#215147 opened Aug 9, 2026 by shiltian Contributor Loading…
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[AArch64] missed fold vector fptoui(fdiv(uitofp(x),uitofp(y))) or fptosi(fdiv(sitofp(x),sitofp(y))) into udiv(x,y) or sdiv(x,y) for sve backend:AArch64
#215146 opened Aug 9, 2026 by dnmohanty Contributor Loading…
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[X86] Fold B + (-C)*A into neg + lea
#215145 opened Aug 9, 2026 by nickitat Member • Draft
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1
[NVPTX] Add NewPM boilerplate to NVPTXForwardParams backend:NVPTX
#215141 opened Aug 9, 2026 by AlexMaclean Member Loading…
@AlexMaclean
3
[AMDGPU][MC] Fix a crash when invalid SDWA encoding is used backend:AMDGPU
#215140 opened Aug 9, 2026 by shiltian Contributor Loading…
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[AMDGPU][MC] Return fail when it is not a VGPR in the decoder backend:AMDGPU
#215136 opened Aug 9, 2026 by shiltian Contributor Loading…
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[ConstraintElimination] Defer removal of simplified ssub.with.overflow llvm:transforms
#215135 opened Aug 9, 2026 by fhahn Contributor Loading…
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[NVPTX] Add NewPM boilerplate to NVPTXImageOptimizer backend:NVPTX
#215133 opened Aug 9, 2026 by AlexMaclean Member Loading…
@AlexMaclean
4
[NVPTX] Add NewPM boilerplate to NVPTXISelDAGToDAG backend:NVPTX
#215132 opened Aug 9, 2026 by AlexMaclean Member Loading…
@AlexMaclean
2
[X86] use vdivph for i8 integer division on avx512fp16 backend:X86
#215131 opened Aug 9, 2026 by AryanBhirud Loading…
1
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[InstCombine] Fold uadd.sat(X, C) - C to umin(X, ~C) llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#215130 opened Aug 9, 2026 by Bagodiya Contributor Loading…
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1
[MLIR][NVVM] Add Rubin extensions to tcgen05.commit Op mlir:llvm mlir:nvvm mlir
#215125 opened Aug 9, 2026 by rajatbajpai Contributor Loading…
@rajatbajpai
1
[CostModel][X86] Add variable divisor div/rem costs for scalar and <=i32 vectors backend:X86 Scheduler Models Accuracy of X86 scheduler models
#215124 opened Aug 9, 2026 by as4230 Contributor • Draft
2
[mlir][arith] Fold scaling_extf and scaling_truncf with constant operands mlir:arith mlir
#215123 opened Aug 9, 2026 by Tim096 Contributor Loading…
2
[InstCombine] Fold X + ((-X) & (C - 1)) to (X + C - 1) & -C llvm:instcombine Covers the InstCombine, InstSimplify and AggressiveInstCombine passes llvm:transforms
#215122 opened Aug 9, 2026 by Bagodiya Contributor Loading…
1
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ProTip! Updated in the last three days: updated:>2026-08-06.